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August 2007
HYS72D 64301H B R- [ 5 / 6 ] - C HYS72D 128300 H BR- [ 5 / 6 ] - C HYS72D 128321 H BR- [ 5 / 6 ] - C HYS72D256x20HBR-[5/6]-C
1 8 4 - P i n R e g i s t e r e d D o u b l e - D a t a - R a t e SD R A M M o d u l e RDIMM DDR SDRAM RoHS Compliant
Internet Data Sheet
Rev. 1.22
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
HYS72D64301HBR-[5/6]-C, HYS72D128300HBR-[5/6]-C, HYS72D128321HBR-[5/6]-C, HYS72D256x20HBR-[5/6]-C Revision History: 2007-08, Rev. 1.22 Page All All All Page 8 Subjects (major changes since last revision) Adapted internet edition Tables updated Qimonda update Subjects (major changes since last revision) Added product types to PC2700R
Previous Revision: 2006-03, Rev. 1.21 Previous Revision: 2006-03, Rev. 1.2
Previous Revision: 2005-12, Rev. 1.1
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 03292006-6N25-8R3I
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
1
1.1
Overview
Features
* 184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for PC, Workstation and Server main memory applications * One rank 64M x72, 128M x72 organization , and two ranks 256M x72 organization * Standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V ( 0.2 V) power supply and +2.6 ( 0.1 V) power supply for DDR400 * Built with DDR SDRAMs in FBGA 60 package * Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) * Auto Refresh (CBR) and Self Refresh * RAS-lockout supported tRAP= tRCD * All inputs and outputs SSTL_2 compatible * Re-drive for all input signals using register and PLL devices. * Serial Presence Detect with E2PROM * Low Profile Modules form factor: 133.35 mm x 28.58 mm (1.1") x 4.00 mm and 133.35 mm x 30.48 mm (1.2") * Standard reference card layout Raw Card A, B, C and F * Gold plated contacts * RoHS Compliant Product1)
TABLE 1
Performance
Part Number Speed Code Speed Grade max. Clock Frequency Component Module @CL3 @CL2.5 @CL2 -5 DDR400B PC3200-3033 -6 DDR333B PC2700-2533 166 166 133 Unit -- -- MHz MHz MHz
fCK3 fCK2.5 fCK2
200 166 133
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
1.2
Description
the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes contain factory programmed configuration data and the second 128 bytes are made available to the customer.
The HYS72D[64/128/256]xxxHBR-[5/6]-C are low-profile versions of the standard Registered DIMM modules with 1.1inch (28.58 mm) and 1.2-inch (30.40 mm) height for Server Applications. The low-profile DIMM versions are available as 64M x72 (512MB), 128M x72 (1 GB), and 256M x72 (2 GB). The memory array is designed with Double-Data-Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to
TABLE 2
Ordering Information
Product Type1) PC3200 (CL=3) HYS72D64301HBR-5-C HYS72D128300HBR-5-C HYS72D128321HBR-5-C HYS72D256320HBR-5-C PC2700 (CL=2.5) HYS72D64301HBR-6-C HYS72D128300HBR-6-C HYS72D128900HBR-6-C HYS72D128321HBR-6-C HYS72D256320HBR-6-C HYS72D256920HBR-6-C PC2700R-25331-A0 PC2700R-25331-C0 PC2700R-25331-C0 PC2700R-25331-B0 PC2700R-25331-F0 PC2700R-25331-F0 one rank 512 MByte Reg. ECC DIMM one rank 1 GByte Reg. ECC DIMM one rank 1 GByte Reg. ECC DIMM two ranks 1 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM 512 MBit (x8) 512 MBit (x4) 512 MBit (x4) 512 MBit (x8) 512 MBit (x4) 512 MBit (x4) PC3200R-30331-A0 PC3200R-30331-C0 PC3200R-30331-B0 PC3200R-30331-F0 one rank 512 MByte Reg. ECC DIMM one rank 1 GByte Reg. ECC DIMM two ranks 1 GByte Reg. ECC DIMM two ranks 2 GByte Reg. ECC DIMM 512 MBit (x8) 512 MBit (x4) 512 MBit (x8) 512 MBit (x4) Compliance Code2) Description SDRAM Technology
1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS72D256320HBR-5-C, indicating Rev.C die are used for SDRAM components. 2) The Compliance Code is printed on the module labels and describes the speed sort (for example "PC2700R"), the latencies (for example "25331" means CAS latency of 2.5 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), SPD code definition version 1, and the Raw Card used for this module.
TABLE 3
Address Format
Density 512 MB 1 GB 1 GB 2 GB Organization 64M x72 128M x72 128M x72 256M x72 Memory Ranks 1 1 2 2 SDRAMs 64M x8 128M x4 64M x8 128M x4 # of SDRAMs 9 18 18 36 # of row/bank/ column bits 13/2/11 13/2/12 13/2/11 13/2/12 Refresh 8K 8K 8K 8K Period 64 ms 64 ms 64 ms 64 ms Interval 7.8 ms 7.8 ms 7.8 ms 7.8 ms
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
2
Pin Configuration
The pin configuration of the Registered DDR SDRAM DIMM is listed by function in Table 4 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 5 and Table 6 respectively. The pin numbering is depicted in Chapter 1.
TABLE 4
Pin Configuration of RDIMM
Pin # 137 138 21 111 Name Pin Type I I I I NC I I NC I I I I Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL - SSTL SSTL SSTL LVCMOS Function
Pin # 37 32 125 29 122 27 141 118 115
Name A4 A5 A6 A7 A8 A9 A10 AP A11 A12
Pin Type I I I I I I I I I I
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Address Bus 11:0
Clock Signals CK0 CK0 CKE0 CKE1 NC 157 158 S0 S1 NC 154 65 63 10 RAS CAS WE RESET Clock Signal Complement Clock Clock Enable Rank 0 Clock Enable Rank 1 Note: 2-rank module Note: 1-rank module Chip Select of Rank 0 Chip Select of Rank 1 Note: 2-ranks module Note: 1-rank module Row Address Strobe Column Address Strobe Write Enable Register Reset Forces registered inputs low Note: For detailed description of the Power Up and Power Management see the Application Note at the end of data sheet Bank Address Bus 1:0 Address Bus 11:0
Control Signals
Address Signal 12 Note: Module based on 256 Mbit or larger dies Note: 128 Mbit based module Address Signal 13 Note: 1 Gbit based module Note: Module based on 512 Mbit or smaller dies Data Bus 63:0
NC 167 A13
NC I
- SSTL
NC
NC
-
Data Signals 2 4 6 8 94 95 98 99 12 13 19 20 105 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Address Signals 59 52 48 43 41 130 BA0 BA1 A0 A1 A2 A3 I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
Pin # 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165
Name DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0
Pin # 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 5 14 25 36 56 67 78 86 47 97
Name DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DM0 DQS9
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0
Check Bits 7:0
Data Strobes 8:0 Note: See block diagram for corresponding DQ signals
Data Mask 0 Note: x8 based module Data Strobe 9 Note: x4 based module Data Mask 1 Note: x8 based module Data Strobe 10 Note: x4 based module Data Mask 2 Note: x8 based module Data Strobe 11 Note: x4 based module
107
DM1 DQS10
119
DM2 DQS11
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
Pin # 129
Name DM3 DQS12
Pin Type I I/O I I/O I I/O I I/O I I/O I I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Mask 3 Note: x8 based module Data Strobe 12 Note: x4 based module Data Mask 4 Note: x8 based module Data Strobe 13 Note: x4 based module Data Mask 5 Note: x8 based module Data Strobe 14 Note: x4 based module Data Mask 6 Note: x8 based module Data Strobe 15 Note: x4 based module Data Mask 7 Note: x8 based module Data Strobe 16 Note: x4 based module Data Mask 8 Note: x8 based module Data Strobe 17 Note: x4 based module Serial Bus Clock Serial Bus Data Slave Address Select Bus 2:0
Pin #
Name
Pin Type PWR
Buffer Type -
Function I/O Driver Power Supply
149
DM4 DQS13
159
DM5 DQS14
169
DM6 DQS15
15, VDDQ 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 7, VDD 38, 46, 70, 85, 108, 120, 148, 168 3 11 18 26 34 42 50 58 66 74 VSS
PWR
-
Power Supply
177
DM7 DQS16
140
DM8 DQS17
GND
-
Ground Plane
EEPROM 92 91 181 182 183 1 184 SCL SDA SA0 SA1 SA2 VREF VDDSPD I I/O I I I AI PWR CMOS OD CMOS CMOS CMOS - - I/O Reference Voltage EEPROM Power Supply
Power Supplies
81 89 93 100
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
Pin # 116 124 132 139 145 152 160 176
Name VSS
Pin Type GND
Buffer Type -
Function Ground Plane
TABLE 5
Abbreviations for Pin Type
Abbreviation Description I O I/O AI PWR GND NU Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Usable (JEDEC Standard) Not Connected (JEDEC Standard)
Other Pins 82 VDDID O OD VDD Identification Note: Pin in tristate, indicating VDD and VDDQ nets connected on PCB Not connected Pins not connected on Qimonda RDIMM's
NC
TABLE 6
Abbreviations for Buffer Type
Abbreviation Description SSTL LV-CMOS CMOS OD Serial Stub Terminalted Logic (SSTL2) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
9, NC 16, 17, 71, 75, 76, 90, 101, 102, 103, 113, 163, 173
NC
-
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HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
FIGURE 1
Pin Configuration 184 Pins, Registered
VREF VSS DQS0 VDD NC VSS DQ09 VDDQ NC DQ10 CKE0 DQ16 DQS2 A9 A7 DQ19 DQ24 DQ25 A4 DQ26 A2 A1 CB01 DQS8 CB02 CB03 -
Pin 001 Pin 003 Pin 005 Pin 007 Pin 009 Pin 011 Pin 013 Pin 015 Pin 017 Pin 019 Pin 021 Pin 023 Pin 025 Pin 027 Pin 029 Pin 031 Pin 033 Pin 035 Pin 037 Pin 039 Pin 041 Pin 043 Pin 045 Pin 047 Pin 049 Pin 051
DQ00 DQ01 DQ02 DQ03 RESET DQ08 DQS1 NC VSS DQ11 VDDQ DQ17 VSS DQ18 VDDQ A5 VSS DQS3 VDD DQ27 VSS CB00 VDD A0 VSS BA1 -
Pin 002 Pin 004 Pin 006 Pin 008 Pin 010 Pin 012 Pin 014 Pin 016 Pin 018 Pin 020 Pin 022 Pin 024 Pin 026 Pin 028 Pin 030 Pin 032 Pin 034 Pin 036 Pin 038 Pin 040 Pin 042 Pin 044 Pin 046 Pin 048 Pin 050 Pin 052
Pin 094 - DQ04 Pin 096 - VDDQ Pin 098 - DQ06 Pin 100 - VSS Pin 102 - NC Pin 104 - VDDQ Pin 106 - DQ13 Pin 108 - VDD Pin 110 - DQ15 Pin 112 - VDDQ Pin 114 - DQ20 Pin 116 - VSS Pin 118 - A11 Pin 120 - VDD Pin 122 Pin 124 Pin 126 Pin 128 Pin 130 Pin 132 Pin 134 Pin 136 Pin 138 Pin 140 Pin 142 Pin 144 A8 VSS DQ28 VDDQ A3 VSS DQ04 VDDQ CK0 DM8/DQS17 CB06 CB07
Pin 093 Pin 095 Pin 097 Pin 099 Pin 101 Pin 103 Pin 105 Pin 107 Pin 109 Pin 111 Pin 113 Pin 115 Pin 117 Pin 119 Pin 121 Pin 123 Pin 125 Pin 127 Pin 129 Pin 131 Pin 133 Pin 135 Pin 137 Pin 139 Pin 141 Pin 143 -
VSS DQ05 DQ00/DQS9 DQ07 NC NC DQ15 DM1/DQS10 DQ14 CKE1/NC NC A12/NC DQ21 DM2/DQS11 DQ22 DQ23 A6 DQ29 DM3/DQS12 DQ30 DQ31 CB5 CK0 VSS A10/AP VDDQ VSS DQ37 DM4/DQS13 DQ39 DQ44 DQ45 S0 DM5/DQS14 DQ46 NC DQ52 A13/NC DM6/DQS15 DQ55 NC DQ61 DM7/DQS16 DQ63 SA0 SA2 MPPD0020
DQ32 DQ33 DQ34 BA0 DQ40 WE CAS DQS5 DQ43 NC DQ49 NC VDDQ DQ50 VSS DQ56 VDD DQ58 VSS SDA -
Pin 053 Pin 055 Pin 057 Pin 059 Pin 061 Pin 063 Pin 065 Pin 067 Pin 069 Pin 071 Pin 073 Pin 075 Pin 077 Pin 079 Pin 081 Pin 083 Pin 085 Pin 087 Pin 089 Pin 091
VDDQ - Pin 054 DQS4 - Pin 056 VSS - Pin 058 DQ35 - Pin 060 VDDQ - Pin 062 DQ41 - Pin 064 VSS - Pin 066 DQ42 - Pin 068 VDD - Pin 070 DQ48 - Pin 072 VSS - Pin 074 NC - Pin 076 DQS6 - Pin 078 DQ51 - Pin 080 VDDID - Pin 082 DQ57 - Pin 084 DQS7 - Pin 086 DQ59 - Pin 088 NC - Pin 090 SCL - Pin 092
Pin 146 - DQ36 Pin 148 - VDD Pin 150 - DQ38 Pin 152 - VSS Pin 154 - RAS Pin 156 - VDDQ Pin 158 - S1/NC Pin 160 - VSS Pin 162 - DQ47 Pin 164 - VDDQ Pin 166 - DQ53 Pin 168 - VDD Pin 170 - DQ54 Pin 172 - VDDQ Pin 174 - DQ60 Pin 176 - VSS Pin 178 - DQ62 Pin 180 - VDDQ Pin 182 - SA1 Pin 184 - VDDSPD
Pin 145 Pin 147 Pin 149 Pin 151 Pin 153 Pin 155 Pin 157 Pin 159 Pin 161 Pin 163 Pin 165 Pin 167 Pin 169 Pin 171 Pin 173 Pin 175 Pin 177 Pin 179 Pin 181 Pin 183 -
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
3
3.1
Electrical Characteristics
Operating Conditions
TABLE 7
Absolute Maximum Ratings
Parameter
Symbol min.
Values typ. - - - - - - 1 50 max.
Unit
Note/ Test Condition - - - - - - - -
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT VIN VDD VDDQ TA TSTG
PD
-0.5 -1 -1 -1 0 -55 - -
VDDQ + 0.5
+3.6 +3.6 +3.6 +70 +150 - -
V V V V C C W mA
IOUT
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit.
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HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
TABLE 8
Electrical Characteristics and DC Operating Conditions
Parameter Symbol Min. Device Supply Voltage Device Supply Voltage Output Supply Voltage Output Supply Voltage EEPROM supply voltage Supply Voltage, I/O Supply Voltage Input Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Values Typ. 2.5 2.6 2.5 2.6 2.5 Max. 2.7 2.7 2.7 2.7 3.6 0 0.5 x VDDQ 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 1.4 2 5 -16.2 -- V V V V V V V V V V V V -- A A mA mA Unit Note/Test Condition1)
VDD VDD VDDQ VDDQ VDDSPD VSS, VSSQ VREF VTT
2.3 2.5 2.3 2.5 2.3 0 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 0.71 -2 -5 -- 16.2
fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3)
-- --
4) 5)
VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and VIN(DC)
CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current Input Leakage Current Output Leakage Current
6) 6) 6)
VID(DC) VIRatio II IOZ
6)7)
8)
Any input 0 V VIN VDD; All other pins not under test = 0 V9) DQs are disabled; 0 V VOUT VDDQ 9) VOUT = 1.95 V VOUT = 0.35 V
Output High Current, Normal IOH Strength Driver Output Low Current, Normal IOL Strength Driver
1) 2) 3) 4) 5) 6) 7) 8)
9)
0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V; DDR400 conditions apply for all clock frequencies above 166 MHz Under all conditions, VDDQ must be less than or equal to VDD. Peak to peak AC noise on VREF may not exceed 2% VREF.DC. VREF is also expected to track noise variations in VDDQ. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. Values are shown per pin.
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
TABLE 9
IDD Conditions
Parameter Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, burst refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet. Symbol
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
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HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
TABLE 10
IDD Specification for HYS72D[64/128/256]xxxHBR-5-C
HYS72D128300HBR-5-C HYS72D128321HBR-5-C HYS72D256320HBR-5-C HYS72D64301HBR-5-C Product Type Unit Note 1)2)
Organization
512 MB x72 1 Rank -5
1 GB x72 1 Rank -5 Max. 1240 1470 440 940 600 530 1050 1510 1560 2120 390 2770 Typ. 1890 2200 670 1360 960 860 1540 2380 2470 3280 640 4450 Max. 2210 2530 780 1510 1120 970 1730 2620 2710 4130 740 5140
1 GB x72 2 Ranks -5 Typ. 1660 1880 670 1360 960 870 1540 1970 2020 2290 640 3010 Max. 1910 2140 780 1510 1120 970 1730 2190 2240 2800 740 3450
2 GB x72 2 Ranks -5 Typ. 3120 3430 1290 2410 1870 1670 2770 3610 3700 4510 1270 5680 Max. 3570 3890 1460 2650 2140 1850 3090 3980 4070 5490 1430 6500 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
Typ. 1050 1270 360 830 510 460 920 1360 1400 1670 330 2390
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) Module IDD is calculated on the basis of component IDD and includes Register and PLL currents 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
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HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
TABLE 11
IDD Specification for HYS72D[64/128/256]xxxHBR-6-C
HYS72D128300HBR-6-C HYS72D128900HBR-6-C HYS72D128321HBR-6-C HYS72D256320HBR-6-C HYS72D256920HBR-6-C HYS72D64301HBR-6-C Product Type Unit Note1)2)
Organization
512 MB x72 1 Rank -6
1 GB x72 1 Rank -6 Max. 1140 1360 410 840 560 500 940 1410 1450 1950 390 2490 Typ. 1790 2000 600 1180 860 770 1370 2090 2180 2930 580 3980 Max. 2020 2330 700 1310 1000 880 1520 2420 2510 3780 680 4580
1 GB x72 2 Ranks -6 Typ. 1530 1700 600 1180 860 770 1370 1740 1790 2040 580 2690 Max. 1720 1940 700 1310 1000 880 1520 1990 2030 2530 680 3070
2 GB x72 2 Ranks -6 Typ. 2860 3060 1120 2060 1630 1460 2440 3150 3240 4000 1110 5040 Max. 3180 3490 1280 2260 1890 1640 2690 3580 3670 4940 1270 5750 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
Typ. 1000 1160 340 740 470 430 830 1210 1250 1510 320 2150
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) Module IDD is calculated on the basis of component IDD and includes Register and PLL currents 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Rev. 1.22, 2007-08 03292006-6N25-8R3I
14
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
3.2
A.C. Timing Parameters
TABLE 12
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol
-5 DDR400B Min. Max. +0.5 0.55 8 12 12 0.55
-6 DDR333 Min. -0.7 0.45 6 6 7.5 0.45 Max. +0.7 0.55 12 12 12 0.55
Unit
Note/ Test Condition 1)
DQ output access time from CK/CK CK high-level width Clock cycle time
tAC tCH tCK
-0.5 0.45 5 6 7.5
ns tCK ns ns ns tCK tCK
2)3)4)5)
2)3)4)5)
CL = 3.0 2)3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5) 2)3)4)5)6)
CK low-level width Auto precharge write recovery + precharge time DQ and DM input hold time DQ and DM input pulse width (each input) DQS output access time from CK/CK
tCL tDAL tDH tDIPW tDQSCK
0.45 (tWR/tCK)+(tRP/tCK) 0.4 1.75 -0.6 0.35 -- 0.72 0.4 0.2 0.2 min. (tCL, tCH) -- 0.6 0.7
-- -- +0.6 -- +0.40 1.25 -- -- -- -- +0.7 -- -- --
0.45 1.75 -0.6 0.35 -- 0.75 0.45 0.2 0.2 min. (tCL, tCH) -- 0.75 0.8 2.2
-- -- +0.6 -- +0.40 1.25 -- -- -- -- +0.7 -- -- --
ns ns ns tCK ns tCK ns tCK tCK ns ns ns ns ns
2)3)4)5) 2)3)4)5)6)
2)3)4)5)
DQS input low (high) pulse width tDQSL,H (write cycle) DQS-DQ skew (DQS and associated DQ signals) Write command to 1 DQS latching transition DQ and DM input setup time DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) Clock Half Period
st
2)3)4)5)
tDQSQ tDQSS tDS tDSH tDSS tHP
TFBGA
2)3)4)5) 2)3)4)5)
2)3)4)5) 2)3)4)5)
2)3)4)5)
2)3)4)5) 2)3)4)5)7)
DQ & DQS high-impedance time tHZ from CK/CK Address and control input hold time tIH
fast slew rate
3)4)5)6)8)
slow slew rate
3)4)5)6)8) 2)3)4)5)9)
Control and Addr. input pulse width (each input)
tIPW
2.2
Rev. 1.22, 2007-08 03292006-6N25-8R3I
15
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
Parameter
Symbol
-5 DDR400B Min. Max. -- -- +0.7 -- -- +0.50 -- 70E+3 -- -- 7.8 -- -- 1.1 0.60 -- -- -- 0.60 -- -- -- --
-6 DDR333 Min. 0.75 0.8 -0.7 2 tHP -tQHS -- tRCD 42 60 18 -- 72 18 0.9 0.40 12 0.25 0 0.40 15 1 75 200 Max. -- -- +0.7 -- -- +0.50 -- 70E+3 -- -- 7.8 -- -- 1.1 0.60 -- -- -- 0.60 -- -- -- --
Unit
Note/ Test Condition 1)
Address and control input setup time
tIS
0.6 0.7
ns ns ns tCK ns ns ns ns ns ns s ns ns tCK tCK ns tCK ns tCK ns tCK ns tCK
fast slew rate
3)4)5)6)8)
slow slew rate
3)4)5)6)8) 2)3)4)5)7)
DQ & DQS low-impedance time from CK/CK Mode register set command cycle time DQ/DQS output hold time from DQS Data hold skew factor Active to Autoprecharge delay Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay Average Periodic Refresh Interval Auto-refresh to Active/Autorefresh command period Precharge command period Read preamble Read postamble Active bank A to Active bank B command Write preamble Write preamble setup time Write postamble Write recovery time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command
tLZ tMRD tQH tQHS tRAP tRAS tRC tRCD tREFI tRFC tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR tXSNR tXSRD
-0.7 2 tHP -tQHS -- tRCD 40 55 15 -- 65 15 0.9 0.40 10 0.25 0 0.40 15 2 75 200
2)3)4)5)
2)3)4)5)
TFBGA 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)
2)3)4)5) 2)3)4)5)10)
2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
2)3)4)5) 2)3)4)5)11) 2)3)4)5)12) 2)3)4)5) 2)3)4)5)
2)3)4)5)
2)3)4)5)
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); DDQ = 2.6 V 0.1 V, DD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
Rev. 1.22, 2007-08 03292006-6N25-8R3I
16
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 9) These parameters guarantee device timing, but they are not necessarily tested on each device. 10) A maximun of eight Autorefresh commands can be posted to any given DDR SDRAM device 11) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending on tDQSS. 12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly.
Rev. 1.22, 2007-08 03292006-6N25-8R3I
17
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
4
SPD Codes
TABLE 13
SPD Codes for HYS72D[64/128/256]3[00/01/20/21]HBR-5-C
HYS72D128321HBR-5-C HYS72D128300HBR-5-C HYS72D64301HBR-5-C
Product Type
Organization
512 MB x72 1 Rank (x8)
1 GByte x72 2 Ranks (x8)
1 GByte x72 1 Rank (x4)
2 GByte x72 2 Ranks (x4) PC3200R- 30331 Rev 1.0 HEX 80 08 07 0D 0C 02 48 00 04 50 70 02 82 04 04 01 0E 04
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device
PC3200R- 30331 Rev 1.0 HEX 80 08 07 0D 0B 01 48 00 04 50 70 02 82 08 08 01 0E 04
PC3200R-30331 PC3200R- 30331 Rev 1.0 HEX 80 08 07 0D 0B 02 48 00 04 50 70 02 82 08 08 01 0E 04 Rev 1.0 HEX 80 08 07 0D 0C 01 48 00 04 50 70 02 82 04 04 01 0E 04
Rev. 1.22, 2007-08 03292006-6N25-8R3I
18
HYS72D256320HBR-5-C
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
HYS72D128321HBR-5-C
HYS72D128300HBR-5-C
Organization
512 MB x72 1 Rank (x8)
HYS72D64301HBR-5-C
Product Type
1 GByte x72 2 Ranks (x8)
1 GByte x72 1 Rank (x4)
2 GByte x72 2 Ranks (x4) PC3200R- 30331 Rev 1.0 HEX 1C 01 02 26 C1 60 70 75 70 3C 28 3C 28 01 60 60 40 40 00 37 41 28 28 50 00 01
Label Code JEDEC SPD Revision Byte# 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 Description CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height
PC3200R- 30331 Rev 1.0 HEX 1C 01 02 26 C1 60 70 75 70 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 01
PC3200R-30331 PC3200R- 30331 Rev 1.0 HEX 1C 01 02 26 C1 60 70 75 70 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 01 Rev 1.0 HEX 1C 01 02 26 C1 60 70 75 70 3C 28 3C 28 01 60 60 40 40 00 37 41 28 28 50 00 01
Rev. 1.22, 2007-08 03292006-6N25-8R3I
19
HYS72D256320HBR-5-C
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
HYS72D128321HBR-5-C
HYS72D128300HBR-5-C
Organization
512 MB x72 1 Rank (x8)
HYS72D64301HBR-5-C
Product Type
1 GByte x72 2 Ranks (x8)
1 GByte x72 1 Rank (x4)
2 GByte x72 2 Ranks (x4) PC3200R- 30331 Rev 1.0 HEX 00 10 42 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 32 35 36 33 32 30 48 42 52 35 43
Label Code JEDEC SPD Revision Byte# 48 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Description not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14
PC3200R- 30331 Rev 1.0 HEX 00 10 C7 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 31 48 42 52 35 43 20
PC3200R-30331 PC3200R- 30331 Rev 1.0 HEX 00 10 C8 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 31 48 42 52 35 43 Rev 1.0 HEX 00 10 41 7F 7F 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 30 30 48 42 52 35 43
Rev. 1.22, 2007-08 03292006-6N25-8R3I
20
HYS72D256320HBR-5-C
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
HYS72D128321HBR-5-C
HYS72D128300HBR-5-C
Organization
512 MB x72 1 Rank (x8)
HYS72D64301HBR-5-C
Product Type
1 GByte x72 2 Ranks (x8)
1 GByte x72 1 Rank (x4)
2 GByte x72 2 Ranks (x4) PC3200R- 30331 Rev 1.0 HEX 20 20 20 20 1x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 87 88 89 90 91 92 93 94 95 - 98 Description Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4)
PC3200R- 30331 Rev 1.0 HEX 20 20 20 20 1x xx xx xx xx 00
PC3200R-30331 PC3200R- 30331 Rev 1.0 HEX 20 20 20 20 1x xx xx xx xx 00 Rev 1.0 HEX 20 20 20 20 1x xx xx xx xx 00
99 - 127 not used
Rev. 1.22, 2007-08 03292006-6N25-8R3I
21
HYS72D256320HBR-5-C
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
TABLE 14
SPD Codes for HYS72D[64/128/256]3[00/01/20/21]HBR-6-C
HYS72D128321HBR-6-C HYS72D128300HBR-6-C HYS72D64301HBR-6-C Product Type HYS72D256320HBR-6-C 2 GByte x72 2 Ranks (x4) PC2700R- 25331 Rev 1.0 HEX 80 08 07 0D 0C 02 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 C1
Organization
512 MB x72 1 Rank (x8)
1 GByte x72 2 Ranks (x8) PC2700R- 25331 Rev 1.0 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 26 C1
1 GByte x72 1 Rank (x4) PC2700R- 25331 Rev 1.0 HEX 80 08 07 0D 0C 01 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 C1
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
PC2700R- 25331 Rev 1.0 HEX 80 08 07 0D 0B 01 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 26 C1
Rev. 1.22, 2007-08 03292006-6N25-8R3I
22
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
HYS72D128321HBR-6-C
HYS72D128300HBR-6-C
Organization
512 MB x72 1 Rank (x8)
HYS72D64301HBR-6-C
Product Type
1 GByte x72 2 Ranks (x8) PC2700R- 25331 Rev 1.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 28 50 00 01 00 10 62 7F 7F
1 GByte x72 1 Rank (x4) PC2700R- 25331 Rev 1.0 HEX 75 70 00 00 48 30 48 2A 01 75 75 45 45 00 3C 48 30 28 50 00 01 00 10 DB 7F 7F
2 GByte x72 2 Ranks (x4) PC2700R- 25331 Rev 1.0 HEX 75 70 00 00 48 30 48 2A 01 75 75 45 45 00 3C 48 30 28 50 00 01 00 10 DC 7F 7F
Label Code JEDEC SPD Revision Byte# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 Description tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2)
PC2700R- 25331 Rev 1.0 HEX 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 28 50 00 01 00 10 61 7F 7F
Rev. 1.22, 2007-08 03292006-6N25-8R3I
23
HYS72D256320HBR-6-C
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
HYS72D128321HBR-6-C
HYS72D128300HBR-6-C
Organization
512 MB x72 1 Rank (x8)
HYS72D64301HBR-6-C
Product Type
1 GByte x72 2 Ranks (x8) PC2700R- 25331 Rev 1.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 32 31 48 42 52 36 43 20 20 20 20 1x
1 GByte x72 1 Rank (x4) PC2700R- 25331 Rev 1.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 31 32 38 33 30 30 48 42 52 36 43 20 20 20 20 1x
2 GByte x72 2 Ranks (x4) PC2700R- 25331 Rev 1.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 32 35 36 33 32 30 48 42 52 36 43 20 20 20 20 1x
Label Code JEDEC SPD Revision Byte# 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Description Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code
PC2700R- 25331 Rev 1.0 HEX 7F 7F 7F 51 00 00 xx 37 32 44 36 34 33 30 31 48 42 52 36 43 20 20 20 20 20 1x
Rev. 1.22, 2007-08 03292006-6N25-8R3I
24
HYS72D256320HBR-6-C
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
HYS72D128321HBR-6-C
HYS72D128300HBR-6-C
Organization
512 MB x72 1 Rank (x8)
HYS72D64301HBR-6-C
Product Type
1 GByte x72 2 Ranks (x8) PC2700R- 25331 Rev 1.0 HEX xx xx xx xx 00
1 GByte x72 1 Rank (x4) PC2700R- 25331 Rev 1.0 HEX xx xx xx xx 00
2 GByte x72 2 Ranks (x4) PC2700R- 25331 Rev 1.0 HEX xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 92 93 94 95 - 98 Description Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4)
PC2700R- 25331 Rev 1.0 HEX xx xx xx xx 00
99 - 127 not used
Rev. 1.22, 2007-08 03292006-6N25-8R3I
25
HYS72D256320HBR-6-C
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
TABLE 15
SPD Codes for HYS72D[128/256]90x0HBR-6-C
HYS72D128900HBR-6-C Product Type HYS72D256920HBR-6-C 2 GByte x72 2 Ranks (x4) PC2700R-25331 Rev 1.0 HEX 80 08 07 0D 0C 02 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 C1 75
Organization
1 GByte x72 1 Rank (x4)
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns]
PC2700R-25331 Rev 1.0 HEX 80 08 07 0D 0C 01 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 C1 75
Rev. 1.22, 2007-08 03292006-6N25-8R3I
26
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
HYS72D128900HBR-6-C
Product Type
Organization
1 GByte x72 1 Rank (x4)
2 GByte x72 2 Ranks (x4) PC2700R-25331 Rev 1.0 HEX 70 00 00 48 30 48 2A 01 75 75 45 45 00 3C 48 30 28 50 00 01 00 10 DC 7F 7F 7F
Label Code JEDEC SPD Revision Byte# 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 66 Description tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3)
PC2700R-25331 Rev 1.0 HEX 70 00 00 48 30 48 2A 01 75 75 45 45 00 3C 48 30 28 50 00 01 00 10 DB 7F 7F 7F
Rev. 1.22, 2007-08 03292006-6N25-8R3I
27
HYS72D256920HBR-6-C
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
HYS72D128900HBR-6-C
Product Type
Organization
1 GByte x72 1 Rank (x4)
2 GByte x72 2 Ranks (x4) PC2700R-25331 Rev 1.0 HEX 7F 7F 51 00 00 xx 37 32 44 32 35 36 39 32 30 48 42 52 36 43 20 20 20 20 1x xx
Label Code JEDEC SPD Revision Byte# 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Description Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code
PC2700R-25331 Rev 1.0 HEX 7F 7F 51 00 00 xx 37 32 44 31 32 38 39 30 30 48 42 52 36 43 20 20 20 20 1x xx
Rev. 1.22, 2007-08 03292006-6N25-8R3I
28
HYS72D256920HBR-6-C
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
HYS72D128900HBR-6-C
Product Type
Organization
1 GByte x72 1 Rank (x4)
2 GByte x72 2 Ranks (x4) PC2700R-25331 Rev 1.0 HEX xx xx xx 00
Label Code JEDEC SPD Revision Byte# 93 94 95 - 98 99 - 127 Description Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4) not used
PC2700R-25331 Rev 1.0 HEX xx xx xx 00
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HYS72D256920HBR-6-C
Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
5
Package Outlines
FIGURE 2
Package Outline Raw Card A - L-DIM-184-21
Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
FIGURE 3
Package Outline Raw Card C - L-DIM-184-22
Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
FIGURE 4
Package Outline Raw Card B - L-DIM-184-23
Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
FIGURE 5
Package Outline Raw Card F - L-DIM-184-25
Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
6
Application Note
Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item 1173) 184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption during low power mode. One feature is externally controlled via a system-generated RESET signal; the second is based on module detection of the input clocks. These enhancements permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked Loop) when the memory is in Self-Refresh mode. The new RESET pin controls power dissipation on the module's registers and ensures that CKE and other SDRAM inputs are maintained at a valid `low' level during power-up and self refresh. When RESET is at a low level, all the register outputs are forced to a low level, and all differential register input receivers are powered down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as an asynchronous signal according to the attached details. Using this function also permits the system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh mode.
TABLE 16
Function for RESET
Register Inputs RESET H H H H L CK Rising Rising L or H High Z X or Hi-Z CK Falling Falling L or H High Z X or Hi-Z Data in (D) H L X X X or Hi-Z Register Outputs1) Data out (Q) H L Qo Illegal input conditions L
1) X : Don't care, Hi-Z : High Impedance, Qo: Data latched at the previous of CK risning and CK falling
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low maintains a high impedance state on the SDRAM DQ, DQS and DM outputs -- where they will remain until activated by a valid `read' cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable. The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made High-Z, and the differential inputs are powered down -- resulting in a total PLL current consumption of less than 1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied inactive on the DIMM. This application note describes the required and optional system sequences associated with the DDR Registered DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2-bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control CKE to one physical DIMM bank through the use of the RESET pin.
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
Power-Up Sequence with RESET -- Required 1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level at the DDR SDRAMs. 2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR SDRAMs. 3. Stabilization of Clocks to the SDRAM The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches 20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 sec prior to SDRAM operation. 4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 5. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-pproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) -- Optional Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking. Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption (RESET low deactivates register CK and CK, data input receivers, and data output drivers). * The system applies Self Refresh entry command. (CKELow, CSLow, RAS Low, CAS Low, WE High) Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares-- with the exception of CKE. * The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-level at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required. * The system turns off clock inputs to the DIMM. (Optional) a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM documentation. b. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during this operation.
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
* The DIMM is in lowest power Self Refresh mode. Self Refresh Exit (RESET low, clocks powered off) -- Optional 1. Stabilization of Clocks to the SDRAM. The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. 2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs. 3. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, RESET timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) -- Optional Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this is an alternate operating mode for these DIMMs. 1. System enters Self Refresh entry command. (CKE Low, CS Low, RAS Low, CAS Low, WE High) Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares -- with the exception of CKE. * The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs. * The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during the operation. * The DIMM is in a low power, Self Refresh mode. Self Refresh Exit (RESET low, clocks running) -- Optional 1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs.
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
2. The system switches RESET to a logic 'high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept an input signal, is t (ACT ) as specified in the register and DIMM documentation. 4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) -- Optional As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) -- Not Permissible In order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the sequence defined in this application note. In the case where RESET remains high and the clocks are powered off, the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM state will result.
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Internet Data Sheet
HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module
Table of Contents
1 1.1 1.2 2 3 3.1 3.2 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 A.C. Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Internet Data Sheet
Edition 2007-08 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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